Increasing formalization of tasks of verification of topology and electrical diagram for CAD-CAM design systems

Aleksandr V. Poluektov; Konstantin V. Zolnikov; A. V. Achkasov; Yu. A. Chevychelov

doi:10.12737/2219-0767-2024-17-1-102-111

UDC 004.9

INCREASING FORMALIZATION OF TASKS OF VERIFICATION OF TOPOLOGY AND ELECTRICAL DIAGRAM FOR CAD-CAM DESIGN SYSTEMS Increasing formalization of tasks of verification of topology and electrical diagram for CAD-CAM design systems

АА Аа

Published in Modeling of systems and processes · Volume 17, Issue 1 · Pages 102–111 · Rubric: Tehnicheskie nauki

DOI: https://doi.org/10.12737/2219-0767-2024-17-1-102-111

Received: 19.03.2024 Accepted: 24.03.2024 Published: 24.03.2024

Authors

Aleksandr V. Poluektov

Konstantin V. Zolnikov

A. V. Achkasov

Yu. A. Chevychelov

Aleksandr V. Poluektov

Voronezh State University of Forestry and Technologies named after G.F. Morozov Voronezh

Konstantin V. Zolnikov

Voronezh State University of Forestry and Technologies named after G.F. Morozov Russian Federation

A. V. Achkasov

Voronezh State University of Forestry and Technologies named after G.F. Morozov Voronezh

Yu. A. Chevychelov

Voronezh State University of Forestry and Technologies named after G.F. Morozov Voronezh

ABSTRACT

The article discusses the study of methods for checking the conformity of the topology and electrical circuit in electronic devices. The authors present a new approach to the analysis and verification of topological structure taking into account electrical characteristics, which leads to increased formalization of problems and provides better optimization of interaction between a person and a computer CAD system. The study includes an analysis of modern methods and tools used in the electronic device design process, and also proposes innovative approaches to ensure consistency between topology and electrical functionality. LVS verification of the project using Caliber, xRC extraction of the project, physical verification of the project using CAD software Cadence Physical Verification System (PVS), LVS verification of the project using PVS are performed. Presents a detailed analysis of the integrated circuit verification process performed using modern CAD tools. The work examines the key stages of verification, including LVS verification of the project using the Caliber tool, xRC extraction of the project, as well as physical verification of the project using the Cadence Physical Verification System (PVS). Particular attention is paid to LVS checks, which are an important design step to ensure compliance with the topology and electrical design. The features of using Caliber to perform LVS checks are discussed, as well as the xRC extraction process to extract parameters of resistors and capacitors. For physical verification of the project, the capabilities of Cadence PVS were used, which provides analysis of compliance of the physical implementation of the circuit with the specified rules. The results obtained and the experience presented in the article can be useful for engineers and researchers involved in the design of integrated circuits, as well as for those interested in the application of modern CAD tools in the field of verification and validation of electronic devices.

KEYWORDS

LVS project verification, xRC project extraction, physical project verification, Cadence Physical Verification System, LVS project verification, Caliber, artificial intelligence.

1. Sozdanie povedencheskoy modeli LDMOS tranzistora na osnove iskusstvennoy MLP neyroseti i ee opisanie na yazyke Verilog-A / S.A. Pobeda, M.I. Chernyh, F.V. Makarenko, K.V. Zol'nikov // Modelirovanie sistem i processov. - 2021. - T. 14, № 2. - S. 28-34. - DOI:https://doi.org/10.12737/2219-0767-2021-14-2-28-34.

2. Analiz problem modelirovaniya elementov KMOP BIS / V.K. Zol'nikov, S.A. Evdokimova, A.V. Fomichev [i dr.] // Modelirovanie sistem i processov. - 2018. - T. 11, № 4. - S. 20-25.

3. Realizaciya optimal'nogo postroeniya kombinacionnogo ustroystva i ocenka nadezhnosti po vyhodnomu napryazheniyu / F.V. Makarenko, A.S. Yagodkin, K.V. Zol'nikov, O.A. Denisova // Modelirovanie sistem i processov. - 2021. - T. 14, № 4. - S. 130-139. - DOI:https://doi.org/10.12737/2219-0767-2021-14-4-130-139.

4. Razrabotka proektnoy sredy i ocenka tehnologichnosti proizvodstva mikroshemy s uchetom stoykosti k special'nym faktoram na primere SBIS 1867C6F / V.A. Sklyar, V.A. Smerek, K.V. Zol'nikov [i dr.] // Modelirovanie sistem i processov. - 2020. - T. 13, № 1. - S. 77-82.

5. Krotkova, N.A. Programmiruemye logicheskie integral'nye shemy (PLIS) / N.A. Krotkova // Nauchnyy al'manah. - 2020. - №. 9-2. - S. 37-39.

6. Sravnenie instrumentov vysokourovnevogo sinteza i konstruirovaniya cifrovoy apparatury / A.S. Kamkin [i dr.] // Trudy Instituta sistemnogo programmirovaniya RAN. - 2022. - T. 34(5). - S. 7-22. - DOI:https://doi.org/10.15514/ISPRAS-2022-34(5)-1.

7. Ivanov, A.A. Programmno-analiticheskiy kompleks SAPR dlya razrabotki elektronnyh ustroystv / A.A. Ivanov, V.B. Petrov // Elektronika i svyaz'. - 2017. - №2 (56). - T. 45-52.

8. Ushenina, I.V. Sovremennye napravleniya razvitiya PLIS arhitektury FPGA / I.V. Ushenina // XXI vek: itogi proshlogo i problemy nastoyaschego plyus. - 2017. - №. 4. - S. 120-124.

9. Smolov, S.A. Obzor metodov izvlecheniya modeley iz HDL-opisaniy / S.A. Smolov // Trudy Instituta sistemnogo programmirovaniya RAN. - 2015. - T. 27(1). - S. 97-124. - DOI:https://doi.org/10.15514/ISPRAS-2015-27(1)-6.

10. Zolotorevich, L.A. Modelirovanie neispravnostey SBIS na povedencheskom urovne na yazyke VHDL / L.A. Zolotorevich // Informatika. - 2005. - T. 3(7). - S.135-145.

11. Corperation A. Cyclone IV FPGA Device Family Overview //Cyclone IV Device Handbook. - 2013. - T. 1.

12. Vtr 8: High-performance cad and customizable FPGA architecture modelling / K.E. Murray [et al.] //ACM Transactions on Reconfigurable Technology and Systems (TRETS). - 2020. - T. 13, №. 2. - S. 1-55.

13. Kalms, L. HiFlipVX: an Open Source High-Level Synthesis FPGA Library for Image Processing / L. Kalms, A. Podlubne, D. Göhringer // Lecture Notes in Computer Science. - 2019. -Vol. 11444. - Pp. 149-164.

14. Kalms, L. HiFlipVX: an Open Source High-Level Synthesis FPGA Library for Image Processing / L. Kalms, A. Podlubne, D. Göhringer // Lecture Notes in Computer Science. - 2019. - Vol. 11444. - Pp. 149-164.

15. An overview of today’s high-level synthesis tools / W. Meeus [et al.] // Design Automation for Embedded Systems. - 2012. - Vol. 16. - Pp. 31-51.

16. Daoud, L. A survey of high level synthesis languages, tools, and compilers for reconfigurable high performance computing / L. Daoud, D. Zydek, H. Selvaraj // Advances in Intelligent Systems and Computing. - 2014. - Vol. 240. - Pp. 483-492.

17. Development and modeling of schematic diagram for the modular reduction device / S.T. Tynymbayev [et al.] // Problems of Informatics. - 2019. - № 4. - Pp.42-52.

18. Navabi, Z. Proektirovanie vstraivaemyh sistem na PLIS / Z. Navabi. - M.: DMK Press, 2016. - 464 s.

19. Allen, P.E. CMOS Analog Circuit Design (The Oxford Series in Electrical and Computer Engineering) / P.E. Allen, D.R. Holberg - Oxford University Press: USA, 2011. - 757 p.

20. Kaeslin, H. Digital Integrated Circuit Design / H. Kaeslin. - New York: Cambridge University Press, 2008. - 845 p.

21. Polyakov, A.K. Yazyki VHDL i VERILOG v proektirovanii cifrovoy apparatury / A.K. Polyakov. - M.: SOLON-Press, 2003. - 320 s.

22. Multiscale Dataflow Programming. - Maxeler Technologies, London, UK, Version 2021.1, May 14, 2021.

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Editor-in-Chief, editorial board chair

GOST

Poluektov A. V., Zolnikov K. V., Achkasov A. V., Chevychelov Y. A. Increasing formalization of tasks of verification of topology and electrical diagram for CAD-CAM design systems // Modeling of systems and processes. 2024. no. 1. pp. 102-111. DOI: https://doi.org/10.12737/2219-0767-2024-17-1-102-111. (Date of access 27.10.2026).

MLA

Aleksandr V. Poluektov, Zolnikov K. V., Achkasov A. V., Chevychelov Y. A.. "Increasing formalization of tasks of verification of topology and electrical diagram for CAD-CAM design systems." Modeling of systems and processes 17.1 (2024): 102-111. DOI: https://doi.org/10.12737/2219-0767-2024-17-1-102-111.

APA

Poluektov A. V., Zolnikov K. V., Achkasov A. V., Chevychelov Y. A. (2024). Increasing formalization of tasks of verification of topology and electrical diagram for CAD-CAM design systems. Modeling of systems and processes, 17(1), 102-111. https://doi.org/10.12737/2219-0767-2024-17-1-102-111

Chicago

Aleksandr V. Poluektov, Zolnikov K. V., Achkasov A. V., Chevychelov Y. A.. "Increasing formalization of tasks of verification of topology and electrical diagram for CAD-CAM design systems." Modeling of systems and processes 17, no. 1 (2024): 102-111. https://doi.org/10.12737/2219-0767-2024-17-1-102-111.

WIKI

{{cite journal | author = Poluektov A. V., Zolnikov K. V., Achkasov A. V., Chevychelov Y. A. | title = Increasing formalization of tasks of verification of topology and electrical diagram for CAD-CAM design systems | journal = Modeling of systems and processes | year = 2024 | volume = 17 | issue = 1 | pages = 102-111 | doi = 10.12737/2219-0767-2024-17-1-102-111 }}

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INCREASING FORMALIZATION OF TASKS OF VERIFICATION OF TOPOLOGY AND ELECTRICAL DIAGRAM FOR CAD-CAM DESIGN SYSTEMS Increasing formalization of tasks of verification of topology and electrical diagram for CAD-CAM design systems

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