UDK 621.3.049.771 Интегральные схемы в соответствии с масштабами интеграции
Verification of silicon digital design kit is a critical task for semiconductor technologies across all scales. The transition to advanced submicron technologies has significantly heightened its relevance due to the escalating complexity and cost of VLSI design. This article presents the development of a set-theoretic model for a test structure aimed at verifying standard digital cell libraries. The proposed model formally describes the hierarchy of components, including elements under test (combinational and sequential), selection and control blocks, input stimulus generation blocks, signal output blocks, and auxiliary hierarchical blocks. The model enables the estimation of the number of inputs and outputs of the verification structure based on library characteristics, such as the number of elements, quantity and bit-width of inputs and outputs, and logical functions of the elements. The results of applying the model are demonstrated using industrial libraries with process nodes of 180 nm, 90 nm, and 28 nm. A 6.4-fold increase in the number of tested elements (from 199 to 1274) results in only a 1.3-fold growth in the total number of inputs/outputs (from 25 to 32), confirming the model’s efficiency. Particular emphasis is placed on reducing the test structure area while maintaining verification completeness.
VLSI, standard cell library, silicon verification, set-theoretic model, design automation, submicron technologies.
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