Russian Federation
AO "Nauchno-issledovatel'skiy institut elektronnoy tehniki"
Russian Federation
Russian Federation
UDK 004.08 Носители вводимых и выводимых данных. Запоминающие среды
The article examines the study of methods for verifying the correspondence of topology and electrical circuit in electronic devices. The authors present a new approach to the analysis and verification of the topological structure, taking into ac-count electrical characteristics, which leads to an increase in the formalization of tasks and provides better optimization of human interaction and a computer CAD system. The research includes an analysis of modern methods and tools used in the development of electronic devices, and also offers innovative approaches to ensuring consistency between to-pology and electrical functionality. LVS verification of the project is performed using Calibre, xRC extraction of the project, physical verification of the project using CADENCE Physical Verification System (PVS), LVS verification of the project using PVS. Presents a detailed analysis of the inte-grated circuit verification process performed using modern CAD tools. The paper discusses the key stages of verifica-tion, including LVS verification of the project using the Cal-ibre tool, xRC extraction of the project, as well as physical verification of the project using Cadence Physical Verifica-tion System (PVS). Special attention is paid to LVS checks, which represent an important design stage that guarantees the compliance of the topology and the electrical circuit. The features of using Calibre to perform LVS checks, as well as the xRC extraction process to extract the parameters of re-sistors and capacitors, are considered. For the physical veri-fication of the project, the capabilities of Cadence PVS were used, which provides an analysis of the compliance of the physical implementation of the scheme with the specified rules. The results obtained and the experience presented in the article can be useful for engineers and researchers in-volved in the design of integrated circuits, as well as for those interested in the use of modern CAD tools in the field of verification and validation of electronic devices
LVS-project Verification, xRC-project extraction, Physical Project Verification, Cadence Physical Verification System, LVS-project verification, Calibre
1. Creation of a behavioral model of an LDMOS transistor based on an artificial MLP neural network and its description in Verilog-A / S.A. Pobeda, M.I. Chernykh, F.V. Makarenko, K.V. Zolnikov // Modeling of systems and processes. – 2021. – T. 14, No. 2. – P. 28-34. – DOI:https://doi.org/10.12737/2219-0767-2021-14-2-28-34.
2. Analysis of problems in modeling CMOS LSI elements / V.K. Zolnikov, S.A. Evdokimova, A.V. Fomichev [et al.] // Modeling of systems and processes. – 2018. – T. 11, No. 4. – P. 20-25.
3. Implementation of the optimal design of a combination device and reliability assessment based on the output voltage / F.V. Makarenko, A.S. Yagodkin, K.V. Zolnikov, O.A. Denisova // Modeling of systems and processes. – 2021. – T. 14, No. 4. – P. 130-139. – DOI:https://doi.org/10.12737/2219-0767-2021-14-4-130-139.
4. Development of a design environment and assessment of the manufacturability of microcircuit production, taking into account resistance to special factors using the example of VLSI 1867Ts6F / V.A. Sklyar, V.A. Smerek, K.V. Zolnikov [et al.] // Modeling of systems and processes. – 2020. – T. 13, No. 1. – P. 77-82.
5. Zolnikov, V.K. Project verification and creation of test sequences for microcircuit design / V.K. Zolnikov, S.A. Evdokimova, T.V. Skvortsova // Modeling of systems and processes. – 2019. – T. 12, No. 1. – P. 10-16.
6. Methods of reliability control in the development of microcircuits / K.V. Zolnikov, S.A. Evdokimova, T.V. Skvortsova, A.E. Gridnev // Modeling of systems and processes. – 2020. – T. 13, No. 1. – P. 39-45.
7. Sukhanov, V.V. Logical design of information support for distributed information systems of critical application / V.V. Sukhanov, O.V. Lankin // Modeling of systems and processes. – 2021. – T. 14, No. 2. – P. 67-73. – DOI:https://doi.org/10.12737/2219-0767-2021-14-2-67-73.
8. Krotkova N. A. Programmable logic integrated circuits (FPGAs) // Scientific almanac. – 2020. – No. 9-2. – pp. 37-39.
9. Kamkin A.S., Chupilko M.M., Lebedev M.S., Smolov S.A., Gaidadzhiev G. Comparison of tools for high-level synthesis and design of digital equipment. Proceedings of the Institute of System Programming of the Russian Academy of Sciences. 2022; 34(5):7-22. https://doi.org/10.15514/ISPRAS-2022-34(5)-1
10. Ivanov A.A., Petrov V.B. CAD software and analytical complex for the development of electronic devices // Electronics and Communications, 2017, No. 2 (56), p. 45-52. 2. Sidorov D.V., Lebedev E.G., Gorbunov A.N.
11. Ushenina I.V. Modern directions of development of FPGA architecture FPGA //XXI century: results of the past and problems of the present plus. – 2017. – No. 4. – pp. 120-124.
12. Smolov S.A. Review of methods for extracting models from HDL descriptions. Proceedings of the Institute of System Programming of the Russian Academy of Sciences. 2015; 27(1):97-124. https://doi.org/10.15514/ISPRAS-2015-27(1)-6
13. Zolotorevich L.A. Behavioral level modeling of VLSI faults in VHDL. Computer science. 2005;(3(7)):135-145.
14. Corperation A. Cyclone IV FPGA Device Family Overview //Cyclone IV Device Handbook. – 2013. – T. 1.
15. Murray KE et al. Vtr 8: High-performance cad and customizable FPGA architecture modeling //ACM Transactions on Reconfigurable Technology and Systems (TRETS). – 2020. – T. 13. – No. 2. – P. 1-55.
16. Kalms L., Podlubne A., Göhringer D. HiFlipVX: an Open Source High-Level Synthesis FPGA Library for Image Processing. Lecture Notes in Computer Science, vol. 11444, 2019, pp. 149-164.
17. Kalms L., Podlubne A., Göhringer D. HiFlipVX: an Open Source High-Level Synthesis FPGA Library for Image Processing. Lecture Notes in Computer Science, vol. 11444, 2019, pp. 149-164.
18. Meeus W., Van Beeck K. et al. An overview of today's high-level synthesis tools. Design Automation for Embedded Systems, vol. 16, 2012, pp. 31-51.
19. Daoud L., Zydek D., Selvaraj H. A survey of high level synthesis languages, tools, and compilers for reconfigurable high performance computing. Advances in Intelligent Systems and Computing, vol. 240, 2014, pp. 483-492.
20. Tynymbayev ST, Aitkhozhayeva Y.Zh, Adilbekkyzy S., et al.Development and modeling of schematic diagram for the modular reduction device. Problems of Informatics, 2019, No. 4, pp.42 – 52.
21. Navabi Z. Design of embedded systems on FPGA: DMK Press. – Moscow, 2016. – 464 p. – ISBN978-5-97060-174-7
22. Allen PE CMOS Analog Circuit Design (The Oxford Series in Electrical and Computer Engineering) / PE Allen, DR Holberg – 3rd edition, – Oxford University Press: USA, 2011. – 757 p.
23. Kaeslin H. Digital Integrated Circuit Design / H. Kaeslin. – New York: Cambridge University Press, 2008. – 845 p.
24. Polyakov A.K. VHDL and VERILOG languages in the design of digital equipment. – M.: SOLON-Press, 2003. – 320 pp.
25. Multiscale Dataflow Programming. Maxeler Technologies, London, UK, Version 2021.1, May 14, 2021
