AO "Nauchno-issledovatel'skiy institut elektronnoy tehniki"
Russian Federation
UDK 621.3.049 Конструирование электрических цепей
The following are considered: the electrical diagram of the project in Virtuoso Schematic Editor, the Launch→ADE L menu, the main window of the Analog Design Environment. The type of analysis and modeling options are set. The time simulation for the selected test scheme is considered. The Analyses→Choos menu item is selected. The type of analy-sis is set. The accuracy of the simulation and all the neces-sary options are shown. The project uses variables that are set using the menu item Variables→Edit.... The menu item Outputs→To Be Plotted→Select On Schematic is selected. The necessary circuits are indicated on the diagram. Tran analysis is introduced as modeling in the time domain (tran-sient analysis). The simulation of an electrical circuit in the time domain is carried out. The output characteristics are obtained as a function of time in the specified range. The transients occurring in the circuit are calculated. A DC anal-ysis was performed – the calculation of the circuit in static mode (DC). All inductors in the netlist have been replaced with a short circuit, and capacitances with a circuit break. Static mode analysis (DC analysis) was performed. The calculation of the working points of the active elements has been performed. The nodes of the circuit potentials, power consumption, transmission characteristics and parameters of noise immunity and logical levels are determined. An analysis of the DC operation point has been made. The characteristics of diodes and transistors at the operating point are determined. AC analysis (low-signal analysis) in the frequency domain was performed. The simulation of an electrical circuit in the frequency domain involves the calcu-lation of output characteristics as functions of frequency. A “config” view has been created for the project schema. In the CIW or Library Manager window, the menu item File→New→Cellview is selected. The library names and cells are specified in the form and are presented in "config", and "Hierarchy – Editor" is selected in the "Application" field
Library Manager, Hierarchy, DC operation, Cell view, Vari-ables, Plotted, Analog, Design, Environment, Modeling, Electrical circuits
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