Russian Federation
The article is devoted to the development of a proprietary CAD system designed for the design of various digital microelectronics devices. The presented works were carried out by VSFEU in cooperation with ROSELECTRONICS Holding. Cadence software was used to simulate a digital microprocessor based on SYNTACORE's 32-bit SCR1 core with the implementation of the IMC instruction set. The synthesis of the RTL model for testing was carried out in automatic mode and included a stage of testing for synthesizability and a stage of direct synthesis. The synthesis was carried out on the basis of standard library elements of the selected technology for the 130 nm process of the HHGRACE factory. For the created model, a test of the connection list (netlist) was performed, while the logical model was replaced by a list of circuits. Then the calculation of the power consumed by the circuit was carried out. At the end of the development, various tests aimed at verifying the correctness of the RTL code were carried out for the ready-made model - tests for compliance with specificity, tests for edge cases (corner case testing), tests based on applied tasks and algorithmic testing (real code testing), as well as tests for pico-high performance and throughput of switches and interfaces.
RTL (Register Transfer Level), computer-aided design (CAD) system, Cadence, System Verilog, product description model.
1. Harakterizaciya i modelirovanie signalov v SAPR / V.A. Sklyar, V.K. Zol'nikov, A.I. Yan'kov [i dr.] // Modelirovanie sistem i processov. - 2018. - T. 11, № 1. - S. 62-67. - DOI:https://doi.org/10.12737/article_5b574c7fd2b815.56868481.
2. Razrabotka proektnoy sredy i ocenka tehnologichnosti proizvodstva mikroshemy s uchetom stoykosti k special'nym faktoram na primere SBIS 1867C6F / V.A. Sklyar, V.A. Smerek, K.V. Zol'nikov [i dr.] // Modelirovanie sistem i processov. - 2020. - T. 13, № 1. - S. 77-82. - DOI:https://doi.org/10.12737/2219-0767-2020-13-1-77-82.
3. Krotkova, N.A. Programmiruemye logicheskie integral'nye shemy (PLIS) / N.A. Krotkova //Nauchnyy al'manah. - 2020. - №. 9-2. - S. 37-39.
4. Metody shemotehnicheskogo modelirovaniya KMOP SBIS s uchetom radiacii / K.V. Zol'nikov [i dr.] // Voprosy atomnoy nauki i tehniki. Seriya: Fizika radiacionnogo vozdeystviya na radioelektronnuyu apparaturu. - 2014. - № 2. - S. 5-9.
5. Sravnenie instrumentov vysokourovnevogo sinteza i konstruirovaniya cifrovoy apparatury / A.S. Kamkin [i dr.] // Trudy Instituta sistemnogo programmirovaniya RAN. - 2022. - T. 34, № 5. - S. 7-22. - DOI:https://doi.org/10.15514/ISPRAS-2022-34(5)-1.
6. Kamkin, A.S. Poisk konfliktov dostupa k dannym v HDL-opisaniyah / A.S. Kamkin, M.S. Lebedev, S.A. Smolov // Trudy Instituta sistemnogo programmirovaniya RAN. - 2019. - T. 31, № 3. - S. 135-144. - DOI:https://doi.org/10.15514/ISPRAS-2019-31(3)-11.
7. Ivanov, A.A. Programmno-analiticheskiy kompleks SAPR dlya razrabotki elektronnyh ustroystv / A.A. Ivanov, V.B. Petrov // Elektronika i svyaz'. - 2017. - №2(56). - C. 45-52.
8. Ushenina, I.V. Sovremennye napravleniya razvitiya PLIS arhitektury FPGA / I.V. Ushenina //XXI vek: itogi proshlogo i problemy nastoyaschego plyus. - 2017. - №. 4. - S. 120-124.
9. Gavrilov, S.V. Reshenie zadach trassirovki mezhsoedineniy s resintezom dlya rekonfiguriruemyh sistem na kristalle / S.V. Gavrilov, D.A. Zheleznikov, V.M. Hvatov // Izvestiya vysshih uchebnyh zavedeniy. Elektronika. - 2017. - T. 22, №. 3. - S. 266-275.
10. Lebedev, M.S. Generaciya funkcional'nyh testov dlya HDL-opisaniy na osnove proverki modeley / M.S. Lebedev, S.A. Smolov // Trudy Instituta sistemnogo programmirovaniya RAN. - 2016. - T. 28, № 4. - S. 41-56. - DOI:https://doi.org/10.15514/ISPRAS-2016-28(4)-3.
11. The performance and energy efficiency potential of FPGAs in scientific computing / T. Nguyen [et al.] // 2020 IEEE/ACM Performance Modeling, Benchmarking and Simulation of High Performance Computer Systems (PMBS). - IEEE, 2020. - Pp. 8-19.
12. Corperation A. Cyclone IV FPGA Device Family Overview // Cyclone IV Device Handbook. - 2013. - T. 1.
13. Vtr 8: High-performance cad and customizable FPGA architecture modelling / K.E. Murray [et al.] // ACM Transactions on Reconfigurable Technology and Systems (TRETS). - 2020. - T. 13, №. 2. - S. 1-55.
14. Kalms, L. HiFlipVX: an Open Source High-Level Synthesis FPGA Library for Image Processing / L. Kalms, A. Podlubne, D. Göhringer // Lecture Notes in Computer Science. - 2019. - Vol. 11444. - Pp. 149-164.
15. Vivado Design Suite User Guide: Model-Based DSP. Design Using System Generator. UG897 (v2020.2), November 18, 2020. - URL: https://www.xilinx.com/content/dam/xilinx/support/documents/sw_manuals/xilinx2020_2/ug897-vivado-sysgen-user.pdf(data obrascheniya: 02.11.2022).
16. FIRRTL. - URL: https://github.com/chipsalliance/firrtl(data obrascheniya: 02.11.2022).
17. DSLX Reference. - URL: https://google.github.io/xls/dslx_reference(data obrascheniya: 02.11.2022).
18. Kalms, L. HiFlipVX: an Open Source High-Level Synthesis FPGA Library for Image Processing / L. Kalms, A. Podlubne, D. Göhringer // Lecture Notes in Computer Science. - 2019. - Vol. 11444. - Pp. 149-164.
19. An overview of today’s high-level synthesis tools / W. Meeus [et al.] // Design Automation for Embedded Systems. - 2012. - Vol. 16. - Pp. 31-51.
20. Design and research of the behavioral model for the modular reduction device / Y.Zh. Aitkhozhayeva [et al.] // Eurasian Physical Technical Journal. - 2020. - Vol. 17. - Pp. 151-156. - DOI:https://doi.org/10.31489/2020No1/151-156.
21. Adilbekkyzy, S. Modeling of the partial reminder former of the modular reduction device / S. Adilbekkyzy, Y.Zh. Aitkhozhayeva, S.T. Tynymbayev // Eurasian Union of Scientists. - 2019. - Vol. 6 (63). - Pp. 47 - 51.
22. Development and modeling of schematic diagram for the modular reduction device / S.T. Tynymbayev, Y.Zh. Aitkhozhayeva, S. Adilbekkyzy [et al.] // Problems of Informatics. - 2019. - No. 4. - Pp. 42-52.
