%0 Journal Article
%T Verilog-A model of the impurity freeze-out in LDD regions at cryogenic temperatures
%A Osykin, A.A.
%A Potupchik, A.G.
%A Panyshev, K.A.
%K SPICE, Verilog-A, CMOS, cryogenic temperature, impurity freeze-out
%J Modeling of systems and processes
%D 2023
%N 16
%P 7
%I FSBE Institution of Higher Education Voronezh State University of Forestry and Technologies named after G.F. Morozov