TY  JOUR
TI  DEVELOPMENT OF THE DESIGN ENVIRONMENT AND ASSESSMENT OF THE MANUFACTURABILITY OF THE CHIP PRODUCTION TAKING INTO ACCOUNT THE RESISTANCE TO SPECIAL FACTORS ON THE EXAMPLE OF VLSI 1867VTS6F
KW  VLSI 1867VC6F
KW  special factors
KW  processability of production
KW  design
KW  design route
KW  microelectronics
KW  special factors.
JO  Modeling of systems and processes
AU  Sklyar, V..
AU  Smerek, V..
AU  Zolnikov, K.V.
AU  Chernov, D.N.
AU  Yagodkin, A.S.
PY  2020
IS  13
PB  FSBE Institution of Higher Education Voronezh State University of Forestry and Technologies named after G.F. Morozov