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DESIGN OF FAULT-TOLERANT CHIP INTERFACES
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DESIGN OF FAULT-TOLERANT CHIP INTERFACES
UDK 62 Инженерное дело. Техника в целом. Транспорт
Zolnikov V. 1
Mozgovoy Nikolay Vasil'evich 2
Grechanyy Sergey Vladimirovich 3
Selyutin Igor' Nikolaevich
Strukov I. 5
Authors:
1.  Voronezh State University of Forestry and Technologies named after G.F. Morozov

Russian Federation
2.  Voronezh State Technical University (kafedra tehnosfernoy i pozharnoy bezopasnosti, professor)

Voronezh, Voronezh, Russian Federation
3.  Voronezh State University of Forestry and Technologies named after G.F. Morozov

5.  Voronezh State University of Forestry and Technologies named after G.F. Morozov

Voronezh, Russian Federation
Type:
Article
DOI:
https://doi.org/10.12737/2219-0767-2020-13-1-17-24
Pages:
from 17 to 24
Status:
Published
Received:
26.05.2020
Accepted:
26.05.2020
Published:
26.05.2020
Subject area:
UDK 62 Инженерное дело. Техника в целом. Транспорт
Language:
Russian
Keywords:
design, fault tolerance, chips, VLSI interface, signal
Abstract and keywords
Abstract (English):
The article discusses the process of designing the interface of fault-tolerant chips. A redundant internal interface is designed for integrating system components on chips into a single information exchange system. The paper describes the interface for the four-channel construction of the VLSI chip of the BMC SNK. Special attention is paid to the description of interface signals.

Keywords:
design, fault tolerance, chips, VLSI interface, signal
References

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